The present invention relates to a memory device. More particularly, the present invention relates to a semiconductor device and a method for fabricating the same wherein a lower part of sidewalls of an active region where a storage node junction region is to be formed is etched, and a portion of the storage node junction region is formed over a device isolation structure to form a vertical SOI (Silicon-on-Insulator) channel region, thereby increasing write/read speed characteristics of the device and improving a refresh characteristic of the device.
When a channel length of a cell transistor is decreased, an ion concentration of a cell channel region is generally increased in order to maintain a threshold voltage of the cell transistor. An electric field in source/drain regions of the cell transistor is enhanced to increase leakage current, which results in degradation of a refresh characteristic of a DRAM structure. Therefore, there is a need for semiconductor devices in which the refresh characteristic is improved.
FIG. 1 is a simplified layout of a conventional semiconductor device, wherein reference numerals 1, 2, and 3 denote an active region, a recess gate region, and a gate region, respectively.
Referring to FIG. 1, a width of the recess gate region 2 is less than that of the gate region 3 by a distance 2D. A distance F is the distance between the neighboring gate regions 3.
FIGS. 2a through 2g are simplified cross-sectional views illustrating a conventional method for fabricating a semiconductor device, wherein FIGS. 2a(i) through 2g(i) are cross-sectional views taken along the line I-I′ of FIG. 1, and FIGS. 2a(ii) through 2g(ii) are cross-sectional views taken along the line II-II′ of FIG. 1.
Referring to FIG. 2a, a device isolation structure 50 is formed on a semiconductor substrate 10 having a pad oxide film 13 and a pad nitride film 15.
Referring to FIG. 2b, the pad nitride film 15 is removed. Ion implantation is performed on the entire surface to form a well and ion implantation region (not shown) in the semiconductor substrate 10. A planarized polysilicon layer 45 is formed on the entire surface of the resultant.
Referring to FIG. 2c, the polysilicon layer 45 and the pad oxide film 13 are etched using a recess gate mask (not shown) as an etching mask to form a polysilicon layer pattern 45a and a pad oxide film pattern 13a to define the recess gate region 2 shown in FIG. 1.
Referring to FIG. 2d, a predetermined thickness of the semiconductor substrate 10 in the recess gate region 2 shown in FIG. 1 is etched to form a first recess 53. The polysilicon layer pattern 45a is removed during a process for forming the first recess 53. In addition, a silicon horn is formed at the semiconductor substrate 10 near to the device isolation structure 50 because the etching rate of the semiconductor substrate 10 near to the device isolation structure 50 is relatively slower than that of the semiconductor substrate 10 far from the device isolation structure 50.
Referring to FIG. 2e, CVD oxide spacers 47 are formed on sidewalls of the first recess 53 and the pad oxide film pattern 13a. The semiconductor substrate 10 exposed at the bottom of the first recess 53 is etched by a predetermined thickness to form a second recess 55.
Referring to FIG. 2f, the spacers 47 and the pad oxide film pattern 13a are removed to expose the semiconductor substrate 10. A gate insulating film 60 is formed on the exposed semiconductor substrate 10. A planarized gate conductive layer 65 filling up the second recess 55 is formed over the gate insulating film 60. A gate hard mask layer 90 is formed over the gate conductive layer 65. Here, the gate conductive layer 65 is a stacked structure of a lower gate conductive layer 70 and an upper gate conductive layer 80.
Referring to 2g, the hard mask layer 90 and the gate conductive layer 65 are etched using a gate mask (not shown) as an etching mask to form a gate 99. Here, a gate channel region (L1+L2+L3), which is disposed under a storage node junction region 5 to be formed in a subsequent process, includes a vertical channel region L1, L3 and a horizontal channel region L2.
The subsequent process for forming storage node junction region 5 may be done by known semiconductor fabrication processes.
According to the above conventional method for fabricating a semiconductor device, the total length (L1+L2+L3) of the gate channel region is enlarged according to increase in a depth of the vertical channel region L1, L3 or a width of the horizontal channel region L2. In particular, in order to increase the width of the horizontal channel region L2, the etching process for the second recess may be performed using an isotropic etching method.
However, increasing the width of the horizontal channel region L2 increases a channel resistance. As a result, the total resistance of a transistor is increased. Accordingly, read/write speed characteristics of the DRAM device are less favorable a driving current of the device is decreased.